Volume 5

December 2014, Volume 5, Number 6

Dynamic Task Scheduling on Multicore Automotive ECUs  
Geetishree Mishra1 and K S Gurumurthy2, 1BMS College of Engineering, India and 2Reva Intitute of Technology, India

Low Power 16-Channel Data Selector for Bio-Medical Applications  
Udary Gnaneshwara Chary1 and K. S. Rao2, 1BVRIT, India and 2Anurag Group of Institutions, India

Performance Analysis of Gated Ring Oscillator Designed for Audio Frequency Range Asynchronous ADC  
Anita Arvind Deshmukh and Raghavendra B. Deshmukh, Visvesvaraya National Institute of Technology, India

Implementation of an Arithmetic Logic Using Area Efficient Carry Lookahead Adder  
Navneet Dubey and Shyam Akashe, ITM University, India

A Charge Recycling Three Phase Dual Rail Pre-Charge Logic Based Flip-Flop  
Kothagudem Mounika, S. Rajendar and R. Naresh, Vardhaman College of Engineering, India

Transistor Level Implementation of Digital Reversible Circuits  
K. Prudhvi Raj and Y. Syamala, Gudlavalleru Engineering College, India

A Novel Low Power High Dynamic Threshold Swing Limited Repeater Insertion for On-Chip Interconnects  
S. Rajendar1, P. Chandrasekhar2, M. Asha Rani3 and Ambati Divya1, 1Vardhaman College of Engineering, India,
2Osmania University, India and 3Jawaharlal Nehru Technological University, India

Performance and Analysis of Ultra Deep Sub Micron Technology Using Complementary Metal Oxide Semiconductor
Shikha Goswami and Shyam Akashe, ITM University, India

October 2014, Volume 5, Number 5

Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effect Transistors in 32 Nanometer
Ali Ghorbani and Ghazaleh Ghorbani, Islamic Azad University, Iran

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique  
Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, Institute of Engineering and Technology, India

Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology  
Mehdi Masoudi1, Milad Mazaheri1, Aliakbar Rezaei1 and Keivan Navi2, 1Science and Research Branch of IAU, Iran and
2Shahid Beheshti University, Iran

A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer  
G. Deepika1, P. Rama Krishna2 and K. S. Rao2, 1RRS College of Engineeering & Technology, India and 2ANURAG Group
of Institutions, India

Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applications  
V. P. Bhale and U. D. Dalal, Sardar Vallabhbhai National Institute of Technology (SVNIT), India

August 2014, Volume 5, Number 4

A 20 Gb/s Injection-Locked Clock and Data Recovery Circuit  
Sara Jafarbeiki1, Khosrow Hajsadeghi1 and Naeeme Modir2, 1Sharif University of Technology, Iran and 2University of Tehran, Iran

CRDOM : Cell Re-Ordering Based Domino On-The-Fly Mapping  
Sai Praveen Kadiyala and Debasis Samanta, Indian Institute of Technology - Kharagpur, India

An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing  
Saumya Vij1, Anu Gupta1 and Alok Mittal2, 1BITS-Pilani, India and 2STMicroelectronics, India

Design and Implementation of 4T, 3T and 3T1D DRAM Cell Design on 32 NM Technology  
Prateek Asthana and Sangeeta Mangesh, JSS Academy of Technical Education, India

Multisim Design and Simulation of 2.2GHz LNA for Wireless Communication  
Oluwajobi F. I, Lawal Wasiu, RUFUS GIWA Polytechnic, Nigeria

June 2014, Volume 5, Number 3

A Novel Approach for Leakage Power Reduction Techniques in 65nm Technologies  
Ajay Kumar Dadoria and Kavita Khare, Maulana Azad National Institute of Technology, India

Compact Low-Power High Slew-Rate CMOS Buffer Amplifier with Power Gating Technique  
Ajay Yadav, Saurabh Khandelwal and Shyam Akashe, ITM University, India

Design of 6-Bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator  
Gulrej Ahmed and Rajendra Kumar Baghel, Maulana Azad National Institute of Technology, India

Design of a Novel Current Balanced Voltage Controlled Delay Element  
Pooja Saxena1, Sudheer K. M2 and V. B. Chandratre2, 1Homi Bhabha National Institute, India and 2Bhabha Atomic Research
Center, India

Impact of Parameter Variations and Optimization on DG-PNIN Tunnel FET  
Priya Jhalani and Manisha Pattanaik, ABV - Indian Institute of Information Technology and Management, India

A Low Power Front End Analog Multiplexing Unit for 12 Lead ECG Signal Acquisition  
D. Hari Priya1, P. Rama Krishna1, A.S.C.S.Sastry2 and K. S. Rao1, 1Anurag Group of Institutions, India and 2K. L University, India

An Efficient Multi Resolution Filter Bank Based on DA Based Multiplication  
Namitha Jose M and U Hari, SRM University, India

Analytical Modeling of Electric Field Distribution in Dual Material Junctionless Surrounding Gate MOSFETs  
P. Suveetha Dhanaselvam and A. Nithya Ananthi, Velammal College of Engineering and Technology, India

FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log
Multiplier and KOM Architecture
Satish S Bhairannawar1, Rathan R2, Raja K B2, Venugopal K R2 and L M Patnaik3, 1Dayanand Sagar College of Engineering,
India, 2University Visvesvaraya College of Engineering, India and 3Indian Institute of Science, India

April 2014, Volume 5, Number 2

BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design  
Uday Panwar and Kavita Khare, MANIT, India

Advanced ATPG Based on Fan, Testability Measures and Fault Reduction  
Vaishali Dhare and Usha Mehta, Nirma University, India

February 2014, Volume 5, Number 1

A Digital Calibration Algorithm with Variable-Amplitude Dithering for Domain-Extended Pipeline ADCs  
Ting Li1 and Chao You2, 1North Dakota State University, USA and 2Nanchang University, China

Cost Effective Test Methodology Using PMU for Automated Test Equipment Systems  
In-Seok Jung1, Yong-Bin Kim1 and Kyung Ki Kim2, 1Northeastern University, USA and 2Daegu University, South Korea