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December 2010, Volume 1, Number 4

A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)  [ pdf ]
Afaq Ahmad, Sultan Qaboos University - Muscat, Sultanate of Oman

A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications  [ pdf ]
S. L. Haridas1 and N. K. Choudhari2, 1B. D. College of Engg., India and 2Smt. Bhagvati Chaturvedi College of Engg., India

Single Electron Transistor: Applications & Problems  [ pdf ]
Om Kumar and Manjit Kaur, Centre for Development of Advanced Computing - Mohali, India

Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low Power applications  [ pdf ]
Shanthala S, Cyril Prasanna Raj P and S.Y.Kulkarni, Nitte Mahalinga Adyanthaya Memorial Institute of Technology-Nitte, India

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory  [ pdf ]
Subashri T, Arunachalam R, Gokul Vinoth Kumar B and Vaidehi V Anna University - Chennai, India

September 2010, Volume 1, Number 3

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor  [ pdf ]
Nikhil Raj, R.K.Sharma, National Institute of Technology-Kurukshetra, India

Heuristic approach to optimize the number of test cases for simple circuits  [ pdf ]
SM. Thamarai, K.Kuppusamy and T. Meyyappan, Alagappa University, India

Low Power Reversible Parallel Binary Adder/Subtractor  [ pdf ]
Rangaraju H G1, Venugopal U2, Muralidhara K N3, Raja K B 2, 1Bangalore Institute of Technology, India, 2University Visvesvaraya College of Engineering, India and 3P E S College of Engineering, India

Statistical Modelling of ft to Process Parameters in 30 NM Gate Length Finfets  [ pdf ]
B. Lakshmi and R. Srinivasan, SSN College of Engineering, India

Design of a High Precision, Wide Ranged Analog Clock Generator with Field Programmability Using Floating-Gate Transistors  [ pdf ]
Garima Kapur, C.M Markan and V. Prem Pyara, Dayalbagh Educational Institute, India

June 2010, Volume 1, Number 2

Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology  [ pdf ]
Ujwala A. Belorkar1 and S.A.Ladhake2, 1Hanuman Vyayam Prasarak Mandals College of Engineering & Technology,India and 2Sipanas College of Engineering & Technology,India

Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication Systems  [ pdf ]
Rajesh Mehra and Swapna Devi , NITTTR, India

Two Dimensional Modeling of Nonuniformly Doped MESFET Under Illumination [ pdf ]
B.K.Mishra, Lochan Jolly and Kalawati Patil, Thakur College of Engg and Technology,India

Minimization of Handoff Latency by Co-ordinate Evaluation Method Using GPS Based Map  [ pdf ]
Debabrata Sarddar1, Joydeep Banerjee1, Souvik Kumar Saha1, Tapas Jana2, Utpal Biswas3 and M.K. Naskar1,1Jadavpur University,India,2Netaji Subhash Engg College,India and 3University of Kalyani, India.

March 2010, Volume 1, Number 1

Design of A Low Power Low Voltage CMOS Opamp [ pdf ]
Ratul Kr. Baruah, Tezpur University, India

QoS Based Capacity Enhancement for WCDMA Network with Coding Scheme  [ pdf ]
K.AYYAPPAN1 and R. KUMAR2 , 1Rajiv Gandhi College of Engineering and Technology, India and 2SRM University, India

Arithmetic Operations in Multi-Valued Logic  [ pdf ]
Vasundara Patel k s1 and k s gurumurthy2, 1Vishweshwaraiah Technological University,India and 2UVCE, Bangalore, India.

Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates  [ pdf ]
K. Ragini1 , Dr. M. Satyam2 and Dr. B.C. Jinaga3 , 1G.Narayanamma Institute of Technology & Science ,India, 2International Institute of Information Technology, India and 3Jawaharlal Nehru Technology University, India


Forthcoming Papers
2010 Volume 1, Number 4
2010 Volume 1, Number 3
2010 Volume 1, Number 2
2010 Volume 1, Number 1