| June 2013, Volume 4, Number 3 |
Design of Three Bit Analog-To-Digital Converter (ADC) Using Spatial Wavefunction Switched (SWS) FETS [Pdf]
Supriya Karmakar, Intel Corporation, USA |
Hardware Efficient Scaling Free Vectoring and Rotational Cordic for DSP Applications [Pdf]
Anita Jain and Kavita Khare, MANIT, India |
Low Power Dual Edge - Triggered Static D Flip-Flop [Pdf]
Anurag, Gurmohan Singh and V. Sulochana, Centre for Development of Advanced Computing, India |
Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion [Pdf]
Damanpreet Kaur and V.Sulochana, Centre for Development of Advanced Computing, India |
CMOS Low Power Cell Library for Digital Design [Pdf]
Kanika Kaur1 and Arti Noor2, 1JJTU, India and 2CDAC, India |
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit [Pdf]
Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H.R.Bhagyalakshmi and M.K. Venkatesha, Visvesvaraya Technological University, India |
Design and Implementation of Car Parking System on FPGA [Pdf]
Ramneet Kaur and Balwinder Singh, Centre for Development of Advanced Computing, India |
A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate [Pdf]
Sadhana Sharma, Abhay Vidyarthi and Shyam Akashe, ITM University, India |
Design of a Programmable Low Power Low Drop-Out Regulator [Pdf]
Jayanthi Vanama1 and G.L.Sampoorna2, 1Powerwave Technologies Pvt. Ltd., India and 2CONEXANT Systems Pvt. Ltd., India |
Design and Performance Analysis of ZBT SRAM Controller [Pdf]
Smriti Sharma and Balwinder Singh, Centre for Development of Advanced Computing, India |
Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter [Pdf]
Arun Kumar Sunaniya and Kavita Khare, MANIT, India |
Power Efficient Carry Propagate Adder [Pdf]
Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, MANIT, India |
Enhancing Multiplier Speed in Fast Fourier Transform Based on Vedic Mathematics [Pdf]
R.P.Meenaakshi Sundari, D.Subathra and M.S.Dhanalaxmi, Sasurie College of Engineering, India |
| April 2013, Volume 4, Number 2 |
An Investigation Into the Relationships Between Logical Operations [Pdf]
Maher A. Nabulsi and Ahmad Abusukhon, Al-Zaytoonah Private University, Jordon |
Evaluation of Optically Illuminated Mosfet Characteristics by Tcad Simulation [Pdf]
Prerana Jain1 and Mishra B.K2, 1SKVM's NMIMS,Vile Parle(W), India and 2Thakur College of Engg and Technology, India |
Establishing A Molecular Communication Channel for Nano Networks [Pdf]
Prachi Raut and Nisha Sarwade, VJTI,India |
FGMOS Based Low-Voltage Low-Power High Output Impedance Regulated Cascode Current Mirror [Pdf]
Abhinav Anand, Sushanta K. Mandal, Anindita Dash and B. Shivalal Patro, KIIT University, India |
Analysis of Small-Signal Parameters of 2-D Modfet with Polarization Effects for Microwave Applications [Pdf]
Ramnish Kumar1, Sandeep K Arya1 and Anil Ahlawat2, 1GJUST-Hisar, India and 2KIET-Ghajiabad, India |
The Design of a Low Power Floating Gate Based Phase Frequency Detector and Charge Pump Implementation [Pdf]
Md Monirul Islam and Ankit Shivhare, KIIT University, India |
Smart Multicrossbar Router Design in NOC [Pdf]
Bhavana Prakash Shrivastava and Kavita Khare, Maulana Azad National Institute of Technology, India |
Design Low Power Encoder for Threshold Inverter Quantization Based Flash ADC Converter [Pdf]
Mamta Gurjar and Shyam Akashe, ITM University, India |
| February 2013, Volume 4, Number 1 |
An Efficient CNTFET Based 7-Input Minority Gate [Pdf]
Samira Shirinabadi Farahani, Ronak Zarhoun, Mohammad Hossein Moaiyeri and Keivan Navi, Shahid Beheshti University, Iran |
Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE [Pdf]
S. Syed Ameer Abbas1, J. Rahumath Nisha1 ,M. Beril Sahaya Mary1 and S. J. Thiruvengadam2, 1Mepco Schlenk Engineering College, India and 2Thiagarajar College of Engineering, India |
Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data [Pdf]
Sunita M.S and Kanchana Bhaaskaran V.S, VIT University, India |
A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology [Pdf]
Tarun Kr. Gupta and Kavita Khare, MANIT, India
|
Dual Field Dual Core Secure Cryptoprocessor on FPGA Platform [Pdf]
C. Veeraraghavan1 and K. Rajendran2, 1Sri Krishna Arts and Science College, India and 2Government Arts College for women, India |
Ternary Tree Asynchronous Interconnect Network for GALS' SOC [Pdf]
Vivek E. Khetade and S.S. Limaye, Rashtrasant Tukdoji Maharaj Nagpur university, India |
A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric [Pdf]
Anil Yadav1, Justin Stander2, Alex K. Jones2 and Gayatri Mehta1, 1University of North Texas, USA and 2University of Pittsburgh, USA
|
Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data [Pdf]
Vaishali Dhare and Usha Mehta, Nirma University, India |
A Multi-Objective Perspective for Operator Scheduling Using Finegrained DVS Architectures [Pdf]
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal, Indian Institute of Technology- Kharagpur, India |
Reduction of Bus Transition for Compressed Code Systems [Pdf]
S. R. Malathi and R. Ramya Asmi, Sri Venkateswara College of Engineering, India |
