Home
Journal Home
Forthcoming Papers
Archives
2012 Volume 3, Number 4
2012 Volume 3, Number 3
2012 Volume 3, Number 2
2012 Volume 3, Number 1
2011 Volume 2
2010 Volume 1
AIRCC Home
|
December 2012, Volume 3, Number 6 |
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture [Pdf]
Hanie Ghaedrahmati and Khosrow Hajsadeghi, Sharif University of Technology, Iran |
Generic System Verilog Universal Verification Methodology Based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPS/SOCS [Pdf]
Abhishek Jain1,2 Giuseppe Bonanno1, Hima Gupta2 and Ajay Goyal3, 1STMicroelectronics, India, 2Jaypee Institute of Information Technology (JIIT), India and 3Cadence Design System, India |
Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates
[Pdf]
H R Bhagyalakshmi and M K Venkatesha, Visvesvaraya Technological University, India |
Performance Evaluation of Throughput Maximization in MC-CDMA for 4G Standard
[Pdf]
Hema Kale1 C.G. Dethe2 and M.M. Mushrif3, 1Jhulelal Institute of Technology, India, 2Priyadarshni Institute of Engineering and Technology, India, 3Yashwantrao Chavan College of Engineering, India |
Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology [Pdf]
Joyashree Bag, Rajanna K M and Subir Kumar Sarkar, Jadavpur University, India |
Design of Reversible Multipliers for Linear Filtering Applications in DSP [Pdf]
Rakshith Saligram1 and Rakshith T.R2, 1B.M.S College of Engineering, India and 2R. V College of Engineering, India |
Synthesis Optimization for Finite State Machine Design in FPGAs [Pdf]
R.Uma and P.Dhavachelvan, Pondicherry University, India |
October 2012, Volume 3, Number 5 |
Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit [Pdf]
Deeprose Subedi and Eugene John, University of Texas at San Antonio, USA |
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme [Pdf]
Majed ValadBeigi, Farshad Safaei and Bahareh Pourshirazi, Shahid Beheshti University G.C, Iran
|
Quaternary Logic and Applications Using Multiple Quantum Well Based SWSFETs [Pdf]
P. Gogna1,2, M. Lingalugari2, J. Chandy2, E. Heller3, E-S. Hasaneen3 and F. Jain2, 1Intel Massachusetts Corp, USA, 2University of Connecticut, USA and 3Minia University, Egypt |
Modified March C-With Concurrency in Testing for Embedded Memory Applications [Pdf]
Muddapu Parvathi1 , N.Vasantha2 and K.Satya Parasad3, 1M.R.I.T.S, India, 2V.C.E, India and 3J.N.T.U.K, India |
Low Power Dynamic Buffer Circuits [Pdf]
Amit Kumar Pandey, Ram Awadh Mishra and Rajendra Kumar Nagaria, M.N.N.I.T, India |
Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs [Pdf]
Santosh Kumar Gupta and S. Baishya, National Institute of Technology - Assam, India |
Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM [Pdf]
Prathima. A1, Kiran Bailey1, K.S.Gurumurthy2, 1BMSCE, India and 2Bangalore University, India |
Design and Implementation of Analog Multiplier with Improved Linearity [Pdf]
Nandini A.S, Sowmya Madhavan and Chirag Sharma, Nitte Meenakshi Institute of Technology, India |
High Fin Width Mosfet Using Gaa Structure [Pdf]
S.L.Tripathi, Ramanuj Mishra and R.A.Mishra, MNNIT, India |
Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications [Pdf]
Sanjeev Rai1, Govind Krishna Pal2, Ram Awadh Mishra1 and Sudarshan Tiwari3, 1Motilal Nehru National Institute of Technology, Allahabad, India, 2Apache Design Solutions, Noida, India, 3Director National Institute of Technology, India |
A XOR Threshold Logic Implementation Through Resonant Tunneling Diode [Pdf]
Nitesh Kumar Dixit and Vinod Kumari, BIET, India |
An Efficient Approach for Four-Layer Channel Routing in VLSI Design [Pdf]
Ajoy Kumar Khan1, Bhaskar Das1 and Tapas Kumar Bayen2, 1Assam University, India and 2N. I. S. T, India |
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology [Pdf]
R .H. Talwekar1 and S.S Limaye2, 1DIMAT, India and 2JIT, India |
Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design [Pdf]
Kiran Agarwal Gupta1, Dinesh K Anvekar2 and Venkateswarlu V3, 1Visvesvaraya Technology University, India, 2 Honeywell Technology Solutions Lab, India and 3UTL Technologies Ltd., India
|
Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System [Pdf]
Chaitali Biswas Dutta1, Partha Garai2 and Amitabha Sinha3, 1Girijananda Chowdhury Institute of Management & Technology, India, 2 Indian Statistical Institute, India and 3West Bengal University of Technology, India |
Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC [Pdf]
Prasun Ghosal and Tuhin Subhra Das, Bengal Engineering and Science University, India |
August 2012, Volume 3, Number 4 |
Deadlock Recovery Technique in Bus Enhanced NoC Architecture [Pdf]
Saeid Sharifian Nia1, Abbas Vafaei1 and Hamid Shahimohamadi2, 1University of Isfahan, Iran and 2Shahid Beheshti University, Iran
|
Design and Implementation A different Architectures of mixcolumn in FPGA [Pdf]
Sliman Arrag, Abdellatif Hamdoun, Abderrahim Tragha and Salah eddine Khamlich, Universite Hassan II Mohammedia, Morocco
|
Delay Error with Meta - Stability Detection and Correction Using CMOS Transmission Logic [Pdf]
Bhawna Kankane, Sandeep Sharma and Navaid Zafar Rizvi, Gautam Buddha University, India
|
FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme [Pdf]
Durga Sowjanya1, K N H Srinivas1 and P Venkata Ganapathi2, 1Sri Vasavi Engineering College, India and 2Quartics Technologies Pvt Ltd, India
|
Improved Algorithm for Throughput Maximization in MC-CDMA [Pdf]
Hema Kale1, C.G. Dethe2 and M.M. Mushrif3,1Jhulelal Institute of Technology, India, 2Priyadarshni Institute of Engineering and Technology, India and
3Yashwantrao Chavan College of Engineering, India
|
Design of Low Power Sigma Delta ADC [Pdf]
Mohammed Arifuddin Sohel1, K. Chenna Kesava Reddy2 and Syed Abdul Sattar3, 1Muffakham Jah College of Engineering and Technology, India, 2TKR College of Engineering, India and 3Royal Institute of Technology and Sciences, India
|
Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits [Pdf]
Rajani H.P.1 and Srimannarayan Kulkarni2, 1KLESs College of Engineering and Technology, India and 2M.S. Ramaiah Institute of Technology, India
|
Universal Rotate Invert Bus Encoding for Low Power VLSI [Pdf]
Shankaranarayana Bhat M and D. Yogitha Jahnavi, Manipal University, India
|
Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSI Interconnects [Pdf]
Devendra Kumar Sharma1, Brajesh Kumar Kaushik2 and R.K.Sharma3, 1Meerut Institute of Engineering and Technology, India, 2Indian Institute of Technology - Roorkee, India and 3National Institute of Technology, India |
Magnetic Resonance Brain Image Segmentation [Pdf]
M.C.Jobin Christ1 and R.M.S.Parvathi2, 1Adhiyamaan College of Engineering, India and 2Sengunthar College of Engineering, India |
Logic Optimization Using Technology Independent MUX Based Adders in FPGA [Pdf]
R.Uma and P.Dhavachelvan, Pondicherry University, India |
June 2012, Volume 3, Number 3 |
A Comparative Study of Ultra-Low Voltage Digital Circuit Design [Pdf]
Aaron Arthurs, Justin Roark, and Jia Di, University of Arkansas, USA |
CNFET Based Basic Gates and a Novel FullAdder Cell [Pdf]
Fazel Sharifi, Amir Momeni and keivan Navi, Shahid Beheshti University, Iran |
Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit [Pdf]
Rajkumar Sarma and Veerati Raju, Lovely Professional University, India |
A Novel Full Adder Cell Based on Carbon Nanotube Field Effect Transistors [Pdf]
Ali Ghorbani, Mehdi Sarkhosh, Elnaz Fayyazi, Neda Mahmoudi and Peiman Keshavarzian, Islamic Azad University, Iran |
A High Efficiency Charge Pump for Low Voltage Devices [Pdf]
Aamna Anil and Ravi Kumar Sharma, Lovely Professional University, India |
Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator [Pdf]
Sushil Kumar and Gurjit Kaur, Gautam Buddha University, India |
Performance Evaluation of CDMA Router for Network-On-Chip [Pdf]
Anant W. Hinganikar1, Mahendra A. Gaikwad1 and Rajendra M. Patrikar2, 1B.D.College of Engineering, India and 2VNIT, India |
Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate (PPPG) [Pdf]
Krishna Murthy M, Gayatri G and Manoj Kumar R, MVGRCE, India |
Design and Performance Analysis of Ultra Low Power 6T SRAM Using Adiabatic Technique [Pdf]
Sunil Jadav, Vikrant and Munish Vashisath, YMCAUS&T, India |
Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog [Pdf]
Addanki Purna Ramesh1, A.V. N. Tilak2 and A.M.Prasad3, 1Sri Vasavi Engineering College, India, 2Gudlavalleru Engineering College, India and 3JNTU, India |
A Review of the 0.09 uM Standard Full Adders [Pdf]
V. Vijay1, J. Prathiba1, S. Niranjan Reddy2 and P. Praveen kumar3, 1Vignan University, India, 2TCS-Chennai, India and 3QIS College of Engg. & Tech, India |
April 2012, Volume 3, Number 2 |
A Systemc/Simulink Co-Simulation Environment of the JPEG Algorithm [Pdf]
Walid Hassairi, Moncef Bousselmi, Mohamed Abid and Carlos Valderrama, UMons University of Mons, Belgium |
Finite State Machine based Vending Machine Controller with Auto-Billing Features [Pdf]
Ana Monga and Balwinder Singh, Center for Development of Advanced Computing, India |
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI Interconnects [Pdf]
S.K.Verma1 and B.K.Kaushik2, 1G. B. Pant Engineering College, India and 2 Indian Institute of Technology - Roorkee, India |
Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology [Pdf]
K. Dhanumjaya, M. Sudha, MN.Giri Prasad and K.Padmaraju, Jawaharlal Nehru Technological University, India |
Microcontroller Based Testing of Digital IP-Core [Pdf]
Amandeep Singh and Balwinder Singh, Center for Development of Advanced Computing, India |
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips [Pdf]
P.A.HarshaVardhini and M.Madhavi Latha, J.N.T.U, India |
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology [Pdf]
Ishit Makwana1 and Vitrag Sheth2, 1Birla Institute of Technology & Science, India and 2Hewlett Packard Global Soft India Pvt. Ltd., India |
Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders [Pdf]
M.Bharathi and K.Neelima, Sree Vidyanikethan Engineering College, India |
FPGA Implementation of ADPLL with Ripple Reduction Techniques [Pdf]
Manoj kumar and Kusum Lata, Indian Institute of Information Technology - Allahabad, India |
Wishbone Bus Architecture - A Survey and Comparison [Pdf]
Mohandeep Sharma and Dilip Kumar, Center for Development of Advanced Computing, India |
An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications [Pdf]
P.Rajeswari1, R.Ramesh2and A.R.Ashwatha1, 1Dayanada Sagar College of Engineering, India and 2Saveetha engineering college, India |
Fault Secure Encoder and Decoder with Clock Gating [Pdf]
N.Kapileswar and P.Vijaya Santhi, NRI Engineering College, India |
A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation [Pdf]
Usha Bhanu.N1 and A.Chilambuchelvan2, 1Anna University, India and 2R.M.D. Engineering college, India |
Design and Noise Optimization of RF Low Noise Amplifier for IEEE Standard 802.11A WLAN [Pdf]
Ravinder Kumar1, Munish Kumar2, and Viranjay M. Srivastava1, 1Jaypee University of Information Technology, India and 2Guru Jambheshwar University of Science and Technology, India |
Threshold Voltage Control Schemes in Finfets [Pdf]
V. Narendar, Ramanuj Mishra, Sanjeev Rai, Nayana R and R. A. Mishra, MNNIT, India |
Design of Near-Threshold CMOS Logic Gates [Pdf]
N. Geetha Rani1, N. Praveen Kumar1, B. Stephen Charles1, P. Chandrasekhar Reddy2 and S.Md.Imran Ali1,1Stanley Stephen College of Engineering & Technology, India and 2JNTUH College of Engineering, India |
Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA [Pdf]
Neenu Joseph and P Nirmal Kumar, Anna University, India |
VHDL Design for Image Segmentation using Gabor filter for Disease Detection [Pdf]
Rucha R. Thakur, Swati R. Dixit and A.Y.Deshmukh, G.H.Raisoni College of Engineering, India |
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design [Pdf]
Subodh Wairya1, Rajendra Kumar Nagaria2 and Sudarshan Tiwari2, 1Institute of Engineering & Technology, India and 2Motilal Nehru National Institute
of Technology, India |
Analog VLSI Implementation of Neural Network Architecture for Signal Processing [Pdf]
Neeraj Chasta1, Sarita Chouhan2and Yogesh Kumar2, 1Mewar University, India and 2MLVTEC, India |
February 2012, Volume 3, Number 1 |
An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance [Pdf]
Brinda Bhowmick and Srimanta Baishya, National Institute of Technology - Silchar, India |
Leakage Power Reduction and Analysis of CMOS Sequential Circuits [Pdf]
M. Janaki Rani1 and S. Malarkann2, 1Sathyabama University, India and 2Manakula Vinayagar Institute of Technology, India |
Self Correcting Memory Design for Fault Free Coding in Progressive Data Streaming Application [Pdf]
Harikishore.Kakarla1, Madhavi Latha.M2 and Habibulla Khan1, 1KL University, India and 2JNTUH, India |
Giga bit per second Differential Scheme for High Speed Interconnect [Pdf]
Mandeep Singh Narula, Pankaj Rakheja and Charu Rana, ITM University, India |
Multi User Detector in CDMA Using Elliptic Curve Cryptography [Pdf]
M. Ranga Rao and B. Prabhakara Rao, JNTU, India |
Design and Modelling of Different SRAM'S Based on CNTFET 32NM Technology [Pdf]
Naagesh. S. Bhat, Mahindra Satyam Ltd., India |
High Speed, Low Power Current Comparators with Hysteresis [Pdf]
Neeraj K. Chasta, Dhirubhai Ambani Institute of Iinformation & Communication Technology, India |
Performance Evaluation of Different SRAM Cell Structures at Different Technologies [Pdf]
Sapna Singh, Neha Arora, Meenakshi Suthar and Neha Gupta, Mody Institute of Technology and Science, India |
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application [Pdf]
Sonal Aggarwal and Rajbir Singh, Kurukshetra university, India |
System on Programable Chip for Performance Estimation of Loom Machine [Pdf]
Gurpreet Singh1 , Ajay Kumar Roy1 , Surekha K S2 , S Pujari3, 1Infosys, India, 2Army Institute of Technology, India and 3Sambalpur University, |
Low Power Folded Cascode OTA [Pdf]
Swati Kundra1, Priyanka Soni1 and Anshul Kundra2, 1Mody Institute of Technology & Science, India and 2Ambedkar Institute of Technology, India |
A 3-14 GHZ Low Noise Amplifier for Ultra Wide Band Applications [Pdf]
Vaithianathan Venkatesan1, Raja Janakiraman2, Srinivasan Raj3, Aishwarya Prabakaran1, Anupreethi Balaji Ranganathan1 and Divya Santhanam1, 1Sri Sivasubramaniya Nadar College of Engineering, India, 2Anna University of Technology - Tiruchirappali, India and 3Sri Sivasubramaniya Nadar College of Engineering, India |
Area, Delay and Power Comparison of Adder Topologies [Pdf]
R.Uma1,Vidya Vijayan2, M. Mohanapriya2 and Sharon Paul2, 1Pondicherry University, India and 2Rajiv Gandhi College of Engineering and Technology, India |
Faster Interleaved Modular Multiplier Based on Sign Detection [Pdf]
Mohamed A. Nassar, and Layla A. A. El-Sayed, Alexandria University, Egypt |
Bus Encoder for Crosstalk Avoidance in RLC Modeled Interconnects [Pdf]
G. Nagendra Babu, Deepika Agarwal, B. K. Kaushik and S. K. Manhas, Indian Institute of Technology - Roorkee, India |
|