Current Issue

October 2018, Volume 9, Number 5

Static Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies
DustenVernor, Santosh Koppa and Eugene John, University of Texas at San Antonio, USA

UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core
Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2, 1University of Colorado, USA and 2Indian Institute of Technology
- Kharagpur, India

August 2018, Volume 9, Number 4

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current
Chien-Cheng Yu1,2, Ming-Chuen Shiau1 and Ching-Chih Tsai2, 1Hsiuping University of Science and Technology, Taiwan and
2National Chung Hsing University, Taiwan

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits
Andrew Suchanek, Zhong Chen and Jia Di, University of Arkansas, USA

June 2018, Volume 9, Number 3

Implementation of Low Power Adiabatic SRAM
Savitha S M1, H P Rajani2 and Shivaling M Hunagund2, 1Visvesvaraya Technological University, India and 2K.L.E.Society's
Dr M S Sheshgiri College of Engineering and Technology, India

VLSI Design of AMBA Based AHB2APB Bridge
Aparna Kharade and V. Jayashree, D.K.T.E. Society's Textile and Engineering Institute, India

Verification of Driver Logic Using AMBA-AXI UVM
Bijal Thakkar and V Jayashree, D.K.T.E. Society's Textile and Engineering Institute, India

Coverage Driven Functional Testing Architecture for Prototyping System Using Synthesizable Active Agent
Dipakkumar Modi and Usha Mehta, Nirma University, India

Performance Evaluation of Low Power Carry Save Adder for VLSI Applications
Divya Tripathi and Subodh Wairya, Institute of Engineering & Technology - Lucknow, India

April 2018, Volume 9, Number 2

Hardware Security in Case of Scan Based Attack on Crypto Hardware
Jayesh Popat and Usha Mehta, Nirma University, India

A Contemporary Survey on Energy Harvesting Techniques for Next Generation Implantable Bio-Medical Devices
J.Jeneetha Jebanazer1 and M.Janakirani2, 1Panimalar Engineering College, India and 2Dr.MGR Educational and Research
Institute University, India

February 2018, Volume 9, Number 1

Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology
T. Suguna and M. Janaki Rani, Dr.M.G. R Educational and Research Institute, India